Lawton Power consumption is an important issue for embedded computing systems. We proposed a novel Low Power Architecture (LPA) cache which reduced dynamic write power dissipation. The new architecture based on separating the sets in the cache. We added a new separating bit named mostly bit to each cache line. The in-coming cache spreading in each set to mostly zero or mostly one by using comparator. This separation reduced the dynamic power by reducing the switching of data from 0s to 1s and vice versa. We used CACTI simulator to evaluate the dynamic write power and SIMPLESCALAR simulator to evaluate the total dynamic power. By using LPA the dynamic write power reduced by 8 % and this value will be increased if the cache size increased.
Keywords: cache, cacti, computer architecture, power consumption, simplescalar.
